85 lines
3.8 KiB
Text
85 lines
3.8 KiB
Text
Pages tables enables each process to have its own private memory space.
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It's slicing the memory into small pages (PGSIZE, 4KiB) so we can
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distribute it to many processes without much fragmentation, and enables
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xv6 a few tricks:
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- mapping the same memory (a trampoline page) in several address spaces
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- guarding kernel and user stacks with an unmapped page
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3.1 Paging hardware
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RISC-V instruction (both user and kernel) manipulate virtual addresses.
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Physical memory (RAM) = physical addresses (phy@ in the notes).
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Virtual memory = fake memory addresses (virt@ in the notes).
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RISC-V page table hardware maps virt@ and phy@.
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XV6 = Sv39 RISC-V = only bottom 39 bits for virt@ (top 25 bits are not used).
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2^39 @ = 2^27 page table entries (PTEs)
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a PTE = 44 bits of physical page number (PPN) + flags
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vocabulary, acronyms, et caetera:
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- physical/virtual addresses = phy@/virt@
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- physical address (what the computer can address) = 2^56 = 65536 TiB
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- virtual address (what a single process can address) = 2^39 = 512 GiB
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- Page Table Entry = PTE
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- Physical Page Number = PPN
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- Page Directory = page table is split into 3 "small page tables" called page directories
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- Translation Look-aside Buffer = TLB
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- Supervisor Address Translation and Protection = satp (it's a register)
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- address space = set of valid virtual addresses in a given page table
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= the kernel also has its own address space
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- User memory = its address space + physical memory allowed by the page table
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- Virtual memory = ideas and techniques associated with managing page tables
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used to achieve isolation & such
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- direct mapping = virt@ == phy@
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virt@ = [ 25-bit EXT ; 27-bit index ; 12-bit offset ]
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↑64 ↑39 ↑12 ↑0
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index = index to the PPN in the page table
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page table = 2^27 entries
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page table entry = [ 44-bit PPN ; 10-bit flags ]
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↑54 ↑10 ↑0
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phy@ = [ 44-bit PPN (indexed by virt@ index) ; 12-bit virt@ offset ]
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↑56 ↑12 ↑0
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virt@ = 39 (usable) bits, phy@ = 56 bits
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Paging hardware translates virt@ with its top 27 of the 39 bits to find a PTE
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IN REAL LIFE there the page table is split into 3 small tables, the index
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is split into 3*9 bits to be used as indexes for these 3 tables.
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These 3 parts can be called "directories":
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1. a "root" (a 4096-byte page table)
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contains 512 PTEs which contain phy@ for next level directory
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2. a "middle" (idem)
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3. a "final"
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In Sv48, there is an extra page table before "root" which takes bits 39
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through 47 of a virt@.
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In case the 3 PTEs points to an invalid page, the page hardware raises a
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"page-fault exception" (execeptions explained in chapter 4).
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RISC-V CPU caches page table entries in a Translation Look-aside Buffer
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(TLB) to avoid costly loads of the PTE from the physical memory.
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PTE flags:
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- PTE_V valid (is the PTE is present or not)
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- PTE_U user mode (if not present, can only be used in supervisor mode)
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- PTE_R read: can the instructions read the page?
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- PTE_W write: can the instructions write the page?
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- PTE_X execute: can the CPU interpret the page's content as instructions and execute them?
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satp register = where to put the phy@ of the root page table to be used by the CPU.
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Once satp, subsequent instructions are interpreted with the provided page table.
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Before setting satp, instructions use phy@.
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Each CPU its own satp so each CPU can handle user code.
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XV6 = 1 page table per process and 1 page table for the kernel
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XV6 kernel page table:
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- direct mapping for most pages
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- no direct mapping for the trampoline page
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- no direct mapping for stacks' pages
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=> these pages are related to the processes (`kstack` in the `proc` structure)
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=> the kstack is followed by an invalid guard page (PTE_V not set)
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to prevent memory corruption from stack overflows
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