37 lines
1.5 KiB
Text
37 lines
1.5 KiB
Text
Pages tables enables each process to have its own private memory space.
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It's slicing the memory into small pages (PGSIZE, 4KiB) so we can
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distribute it to many processes without much fragmentation, and enables
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xv6 a few tricks:
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- mapping the same memory (a trampoline page) in several address spaces
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- guarding kernel and user stacks with an unmapped page
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3.1 Paging hardware
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RISC-V instruction (both user and kernel) manipulate virtual addresses.
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Physical memory (RAM) = physical addresses (phy@ in the notes).
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Virtual memory = fake memory addresses (virt@ in the notes).
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RISC-V page table hardware maps virt@ and phy@.
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XV6 = Sv39 RISC-V = only bottom 39 bits for virt@ (top 25 bits are not used).
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2^39 @ = 2^27 page table entries (PTEs)
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a PTE = 44 bits of physical page number (PPN) + flags
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vocabulary, acronyms, et caetera:
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- physical/virtual addresses = phy@/virt@
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- Page Table Entry = PTE
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- Physical Page Number = PPN
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virt@ = [ 25-bit EXT ; 27-bit index ; 12-bit offset ]
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↑64 ↑39 ↑12 ↑0
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index = index to the PPN in the page table
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page table = 2^27 entries
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page table entry = [ 44-bit PPN ; 10-bit flags ]
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↑54 ↑10 ↑0
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phy@ = [ 44-bit PPN (indexed by virt@ index) ; 12-bit virt@ offset ]
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↑56 ↑12 ↑0
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virt@ = 39 (usable) bits, phy@ = 56 bits
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Paging hardware translates virt@ with its top 27 of the 39 bits to find a PTE
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