switch from machine-mode to supervisor timer interrupts.
this requires qemu version >= 7.2.
This commit is contained in:
Robert Morris
parent
5a1a4d45a4
commit
92e60dd833
5 changed files with 57 additions and 109 deletions
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@ -62,39 +62,3 @@ kernelvec:
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# return to whatever we were doing in the kernel.
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sret
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#
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# machine-mode timer interrupt.
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#
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.globl timervec
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.align 4
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timervec:
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# start.c has set up the memory that mscratch points to:
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# scratch[0,8,16] : register save area.
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# scratch[24] : address of CLINT's MTIMECMP register.
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# scratch[32] : desired interval between interrupts.
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csrrw a0, mscratch, a0
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sd a1, 0(a0)
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sd a2, 8(a0)
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sd a3, 16(a0)
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# schedule the next timer interrupt
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# by adding interval to mtimecmp.
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ld a1, 24(a0) # CLINT_MTIMECMP(hart)
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ld a2, 32(a0) # interval
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ld a3, 0(a1)
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add a3, a3, a2
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sd a3, 0(a1)
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# arrange for a supervisor software interrupt
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# after this handler returns.
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li a1, 2
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csrw sip, a1
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ld a3, 16(a0)
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ld a2, 8(a0)
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ld a1, 0(a0)
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csrrw a0, mscratch, a0
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mret
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@ -25,11 +25,6 @@
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#define VIRTIO0 0x10001000
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#define VIRTIO0_IRQ 1
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// core local interruptor (CLINT), which contains the timer.
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#define CLINT 0x2000000L
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#define CLINT_MTIMECMP(hartid) (CLINT + 0x4000 + 8*(hartid))
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#define CLINT_MTIME (CLINT + 0xBFF8) // cycles since boot.
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// qemu puts platform-level interrupt controller (PLIC) here.
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#define PLIC 0x0c000000L
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#define PLIC_PRIORITY (PLIC + 0x0)
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@ -96,9 +96,7 @@ w_sie(uint64 x)
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}
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// Machine-mode Interrupt Enable
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#define MIE_MEIE (1L << 11) // external
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#define MIE_MTIE (1L << 7) // timer
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#define MIE_MSIE (1L << 3) // software
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#define MIE_STIE (1L << 5) // supervisor timer
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static inline uint64
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r_mie()
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{
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@ -176,11 +174,34 @@ r_stvec()
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return x;
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}
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// Machine-mode interrupt vector
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static inline void
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w_mtvec(uint64 x)
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// Supervisor Timer Comparison Register
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static inline uint64
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r_stimecmp()
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{
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asm volatile("csrw mtvec, %0" : : "r" (x));
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uint64 x;
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asm volatile("csrr %0, stimecmp" : "=r" (x) );
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return x;
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}
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static inline void
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w_stimecmp(uint64 x)
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{
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asm volatile("csrw stimecmp, %0" : : "r" (x));
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}
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// Machine Environment Configuration Register
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static inline uint64
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r_menvcfg()
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{
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uint64 x;
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asm volatile("csrr %0, menvcfg" : "=r" (x) );
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return x;
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}
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static inline void
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w_menvcfg(uint64 x)
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{
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asm volatile("csrw menvcfg, %0" : : "r" (x));
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}
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// Physical Memory Protection
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@ -217,12 +238,6 @@ r_satp()
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return x;
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}
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static inline void
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w_mscratch(uint64 x)
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{
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asm volatile("csrw mscratch, %0" : : "r" (x));
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}
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// Supervisor Trap Cause
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static inline uint64
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r_scause()
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@ -10,12 +10,6 @@ void timerinit();
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// entry.S needs one stack per CPU.
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__attribute__ ((aligned (16))) char stack0[4096 * NCPU];
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// a scratch area per CPU for machine-mode timer interrupts.
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uint64 timer_scratch[NCPU][5];
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// assembly code in kernelvec.S for machine-mode timer interrupt.
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extern void timervec();
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// entry.S jumps here in machine mode on stack0.
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void
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start()
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@ -54,36 +48,19 @@ start()
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asm volatile("mret");
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}
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// arrange to receive timer interrupts.
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// they will arrive in machine mode
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// at timervec in kernelvec.S,
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// which turns them into software interrupts for
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// devintr() in trap.c.
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// ask each hart to generate timer interrupts.
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void
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timerinit()
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{
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// each CPU has a separate source of timer interrupts.
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int id = r_mhartid();
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// ask the CLINT for a timer interrupt.
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int interval = 1000000; // cycles; about 1/10th second in qemu.
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*(uint64*)CLINT_MTIMECMP(id) = *(uint64*)CLINT_MTIME + interval;
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// prepare information in scratch[] for timervec.
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// scratch[0..2] : space for timervec to save registers.
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// scratch[3] : address of CLINT MTIMECMP register.
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// scratch[4] : desired interval (in cycles) between timer interrupts.
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uint64 *scratch = &timer_scratch[id][0];
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scratch[3] = CLINT_MTIMECMP(id);
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scratch[4] = interval;
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w_mscratch((uint64)scratch);
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// set the machine-mode trap handler.
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w_mtvec((uint64)timervec);
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// enable machine-mode interrupts.
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w_mstatus(r_mstatus() | MSTATUS_MIE);
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// enable machine-mode timer interrupts.
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w_mie(r_mie() | MIE_MTIE);
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// enable supervisor-mode timer interrupts.
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w_mie(r_mie() | MIE_STIE);
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// enable the sstc extension (i.e. stimecmp).
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w_menvcfg(r_menvcfg() | (1L << 63));
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// allow supervisor to use stimecmp and time.
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w_mcounteren(r_mcounteren() | 2);
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// ask for the very first timer interrupt.
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w_stimecmp(r_time() + 1000000);
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}
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@ -145,8 +145,8 @@ kerneltrap()
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panic("kerneltrap: interrupts enabled");
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if((which_dev = devintr()) == 0){
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printf("scause 0x%lx\n", scause);
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printf("sepc=0x%lx stval=0x%lx\n", r_sepc(), r_stval());
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// interrupt or trap from an unknown source
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printf("scause=0x%lx sepc=0x%lx stval=0x%lx\n", scause, r_sepc(), r_stval());
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panic("kerneltrap");
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}
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@ -163,10 +163,17 @@ kerneltrap()
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void
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clockintr()
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{
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acquire(&tickslock);
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ticks++;
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wakeup(&ticks);
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release(&tickslock);
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if(cpuid() == 0){
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acquire(&tickslock);
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ticks++;
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wakeup(&ticks);
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release(&tickslock);
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}
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// ask for the next timer interrupt. this also clears
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// the interrupt request. 1000000 is about a tenth
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// of a second.
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w_stimecmp(r_time() + 1000000);
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}
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// check if it's an external interrupt or software interrupt,
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@ -179,8 +186,7 @@ devintr()
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{
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uint64 scause = r_scause();
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if((scause & 0x8000000000000000L) &&
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(scause & 0xff) == 9){
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if(scause == 0x8000000000000009L){
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// this is a supervisor external interrupt, via PLIC.
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// irq indicates which device interrupted.
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@ -201,18 +207,9 @@ devintr()
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plic_complete(irq);
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return 1;
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} else if(scause == 0x8000000000000001L){
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// software interrupt from a machine-mode timer interrupt,
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// forwarded by timervec in kernelvec.S.
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if(cpuid() == 0){
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clockintr();
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}
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// acknowledge the software interrupt by clearing
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// the SSIP bit in sip.
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w_sip(r_sip() & ~2);
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} else if(scause == 0x8000000000000005L){
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// timer interrupt.
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clockintr();
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return 2;
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} else {
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return 0;
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