start on MP; detect MP configuration
This commit is contained in:
kaashoek
parent
ae6e8aa730
commit
7baa34a421
7 changed files with 323 additions and 2 deletions
2
Makefile
2
Makefile
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@ -1,5 +1,5 @@
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OBJS = main.o console.o string.o kalloc.o proc.o trapasm.o trap.o vectors.o \
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syscall.o ide.o picirq.o
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syscall.o ide.o picirq.o mp.o
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CC = i386-jos-elf-gcc
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LD = i386-jos-elf-ld
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5
defs.h
5
defs.h
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@ -21,6 +21,7 @@ void tinit(void);
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// string.c
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void * memcpy(void *dst, void *src, unsigned n);
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void * memset(void *dst, int c, unsigned n);
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int memcmp(const void *v1, const void *v2, unsigned n);
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// syscall.c
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void syscall(void);
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@ -28,3 +29,7 @@ void syscall(void);
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// picirq.c
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void irq_setmask_8259A(uint16_t mask);
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void pic_init(void);
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// mp.c
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void mpinit(void);
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3
main.c
3
main.c
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@ -22,6 +22,7 @@ main()
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cprintf("\nxV6\n\n");
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mpinit(); // multiprocessor
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kinit(); // physical memory allocator
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tinit(); // traps and interrupts
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pic_init();
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@ -47,7 +48,7 @@ main()
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write_eflags(read_eflags() | FL_IF);
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irq_setmask_8259A(0);
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#if 1
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#if 0
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ide_read(0, buf, 1);
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cprintf("sec0.0 %x\n", buf[0] & 0xff);
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#endif
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3
memlayout.h
Normal file
3
memlayout.h
Normal file
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@ -0,0 +1,3 @@
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#define EXTPHYSMEM 0x100000
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#define KADDR(a) ((void *) a)
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139
mp.c
Normal file
139
mp.c
Normal file
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@ -0,0 +1,139 @@
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#include "types.h"
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#include "mp.h"
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#include "defs.h"
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#include "memlayout.h"
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static struct _MP_* _mp_; /* The MP floating point structure */
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static int ncpu;
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static struct _MP_*
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mp_scan(uint8_t *addr, int len)
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{
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uint8_t *e, *p, sum;
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int i;
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cprintf("scanning: 0x%x\n", (uint32_t)addr);
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e = addr+len;
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for(p = addr; p < e; p += sizeof(struct _MP_)){
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if(memcmp(p, "_MP_", 4))
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continue;
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sum = 0;
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for(i = 0; i < sizeof(struct _MP_); i++)
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sum += p[i];
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if(sum == 0)
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return (struct _MP_ *)p;
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}
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return 0;
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}
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static struct _MP_*
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mp_search(void)
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{
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uint8_t *bda;
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uint32_t p;
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struct _MP_ *mp;
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/*
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* Search for the MP Floating Pointer Structure, which according to the
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* spec is in one of the following three locations:
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* 1) in the first KB of the EBDA;
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* 2) in the last KB of system base memory;
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* 3) in the BIOS ROM between 0xE0000 and 0xFFFFF.
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*/
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bda = KADDR(0x400);
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if((p = (bda[0x0F]<<8)|bda[0x0E])){
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if((mp = mp_scan(KADDR(p), 1024)))
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return mp;
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}
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else{
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p = ((bda[0x14]<<8)|bda[0x13])*1024;
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if((mp = mp_scan(KADDR(p-1024), 1024)))
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return mp;
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}
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return mp_scan(KADDR(0xF0000), 0x10000);
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}
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static int
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mp_detect(void)
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{
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struct PCMP *pcmp;
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uint8_t *p, sum;
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uint32_t length;
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/*
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* Search for an MP configuration table. For now,
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* don't accept the default configurations (physaddr == 0).
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* Check for correct signature, calculate the checksum and,
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* if correct, check the version.
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* To do: check extended table checksum.
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*/
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if((_mp_ = mp_search()) == 0 || _mp_->physaddr == 0)
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return 1;
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pcmp = KADDR(_mp_->physaddr);
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if(memcmp(pcmp, "PCMP", 4))
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return 2;
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length = pcmp->length;
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sum = 0;
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for(p = (uint8_t*)pcmp; length; length--)
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sum += *p++;
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if(sum || (pcmp->version != 1 && pcmp->version != 4))
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return 3;
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cprintf("MP spec rev #: %x\n", _mp_->specrev);
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return 0;
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}
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void
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mpinit()
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{
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int r;
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uint8_t *p, *e;
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struct PCMP *pcmp;
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ncpu = 0;
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if ((r = mp_detect()) != 0) return;
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cprintf ("This computer is multiprocessor!\n");
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/*
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* Run through the table saving information needed for starting
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* application processors and initialising any I/O APICs. The table
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* is guaranteed to be in order such that only one pass is necessary.
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*/
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pcmp = KADDR(_mp_->physaddr);
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p = ((uint8_t*)pcmp)+sizeof(struct PCMP);
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e = ((uint8_t*)pcmp)+pcmp->length;
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while(p < e) {
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switch(*p){
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case PcmpPROCESSOR:
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cprintf("a processor\n");
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ncpu++;
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p += sizeof(struct PCMPprocessor);
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continue;
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case PcmpBUS:
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cprintf("a bus\n");
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p += sizeof(struct PCMPbus);
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continue;
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case PcmpIOAPIC:
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cprintf("an IO APIC\n");
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p += sizeof(struct PCMPioapic);
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continue;
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case PcmpIOINTR:
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cprintf("an IO interrupt assignment\n");
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p += sizeof(struct PCMPintr);
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continue;
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default:
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cprintf("mpinit: unknown PCMP type 0x%x (e-p 0x%x)\n", *p, e-p);
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while(p < e){
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cprintf("%uX ", *p);
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p++;
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}
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break;
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}
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}
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cprintf("ncpu: %d\n", ncpu);
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}
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158
mp.h
Normal file
158
mp.h
Normal file
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@ -0,0 +1,158 @@
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/*
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* MultiProcessor Specification Version 1.[14].
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*/
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struct _MP_ { /* floating pointer */
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uint8_t signature[4]; /* "_MP_" */
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physaddr_t physaddr; /* physical address of MP configuration table */
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uint8_t length; /* 1 */
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uint8_t specrev; /* [14] */
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uint8_t checksum; /* all bytes must add up to 0 */
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uint8_t type; /* MP system configuration type */
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uint8_t imcrp;
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uint8_t reserved[3];
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};
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struct PCMP { /* configuration table header */
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uint8_t signature[4]; /* "PCMP" */
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uint16_t length; /* total table length */
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uint8_t version; /* [14] */
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uint8_t checksum; /* all bytes must add up to 0 */
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uint8_t product[20]; /* product id */
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uintptr_t oemtable; /* OEM table pointer */
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uint16_t oemlength; /* OEM table length */
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uint16_t entry; /* entry count */
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uintptr_t lapicbase; /* address of local APIC */
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uint16_t xlength; /* extended table length */
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uint8_t xchecksum; /* extended table checksum */
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uint8_t reserved;
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};
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struct PCMPprocessor { /* processor table entry */
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uint8_t type; /* entry type (0) */
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uint8_t apicno; /* local APIC id */
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uint8_t version; /* local APIC verison */
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uint8_t flags; /* CPU flags */
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uint8_t signature[4]; /* CPU signature */
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uint32_t feature; /* feature flags from CPUID instruction */
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uint8_t reserved[8];
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};
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struct PCMPbus { /* bus table entry */
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uint8_t type; /* entry type (1) */
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uint8_t busno; /* bus id */
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char string[6]; /* bus type string */
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};
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struct PCMPioapic { /* I/O APIC table entry */
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uint8_t type; /* entry type (2) */
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uint8_t apicno; /* I/O APIC id */
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uint8_t version; /* I/O APIC version */
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uint8_t flags; /* I/O APIC flags */
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uintptr_t addr; /* I/O APIC address */
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};
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struct PCMPintr { /* interrupt table entry */
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uint8_t type; /* entry type ([34]) */
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uint8_t intr; /* interrupt type */
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uint16_t flags; /* interrupt flag */
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uint8_t busno; /* source bus id */
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uint8_t irq; /* source bus irq */
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uint8_t apicno; /* destination APIC id */
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uint8_t intin; /* destination APIC [L]INTIN# */
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};
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struct PCMPsasm { /* system address space mapping entry */
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uint8_t type; /* entry type (128) */
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uint8_t length; /* of this entry (20) */
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uint8_t busno; /* bus id */
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uint8_t addrtype;
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uintptr_t addrbase[2];
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uint32_t addrlength[2];
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};
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struct PCMPhierarchy { /* bus hierarchy descriptor entry */
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uint8_t type; /* entry type (129) */
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uint8_t length; /* of this entry (8) */
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uint8_t busno; /* bus id */
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uint8_t info; /* bus info */
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uint8_t parent; /* parent bus */
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uint8_t reserved[3];
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};
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struct PCMPcbasm { /* compatibility bus address space modifier entry */
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uint8_t type; /* entry type (130) */
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uint8_t length; /* of this entry (8) */
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uint8_t busno; /* bus id */
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uint8_t modifier; /* address modifier */
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uint32_t range; /* predefined range list */
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};
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enum { /* table entry types */
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PcmpPROCESSOR = 0x00, /* one entry per processor */
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PcmpBUS = 0x01, /* one entry per bus */
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PcmpIOAPIC = 0x02, /* one entry per I/O APIC */
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PcmpIOINTR = 0x03, /* one entry per bus interrupt source */
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PcmpLINTR = 0x04, /* one entry per system interrupt source */
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PcmpSASM = 0x80,
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PcmpHIERARCHY = 0x81,
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PcmpCBASM = 0x82,
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/* PCMPprocessor and PCMPioapic flags */
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PcmpEN = 0x01, /* enabled */
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PcmpBP = 0x02, /* bootstrap processor */
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/* PCMPiointr and PCMPlintr flags */
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PcmpPOMASK = 0x03, /* polarity conforms to specifications of bus */
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PcmpHIGH = 0x01, /* active high */
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PcmpLOW = 0x03, /* active low */
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PcmpELMASK = 0x0C, /* trigger mode of APIC input signals */
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PcmpEDGE = 0x04, /* edge-triggered */
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PcmpLEVEL = 0x0C, /* level-triggered */
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/* PCMPiointr and PCMPlintr interrupt type */
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PcmpINT = 0x00, /* vectored interrupt from APIC Rdt */
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PcmpNMI = 0x01, /* non-maskable interrupt */
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PcmpSMI = 0x02, /* system management interrupt */
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PcmpExtINT = 0x03, /* vectored interrupt from external PIC */
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/* PCMPsasm addrtype */
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PcmpIOADDR = 0x00, /* I/O address */
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PcmpMADDR = 0x01, /* memory address */
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PcmpPADDR = 0x02, /* prefetch address */
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/* PCMPhierarchy info */
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PcmpSD = 0x01, /* subtractive decode bus */
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/* PCMPcbasm modifier */
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PcmpPR = 0x01, /* predefined range list */
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};
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/*
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* Common bits for
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* I/O APIC Redirection Table Entry;
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* Local APIC Local Interrupt Vector Table;
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* Local APIC Inter-Processor Interrupt;
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* Local APIC Timer Vector Table.
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*/
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enum {
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ApicFIXED = 0x00000000, /* [10:8] Delivery Mode */
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ApicLOWEST = 0x00000100, /* Lowest priority */
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ApicSMI = 0x00000200, /* System Management Interrupt */
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ApicRR = 0x00000300, /* Remote Read */
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ApicNMI = 0x00000400,
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ApicINIT = 0x00000500, /* INIT/RESET */
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ApicSTARTUP = 0x00000600, /* Startup IPI */
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ApicExtINT = 0x00000700,
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ApicPHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */
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ApicLOGICAL = 0x00000800,
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ApicDELIVS = 0x00001000, /* [12] Delivery Status (RO) */
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ApicHIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */
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ApicLOW = 0x00002000,
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ApicRemoteIRR = 0x00004000, /* [14] Remote IRR (RO) */
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ApicEDGE = 0x00000000, /* [15] Trigger Mode (RW) */
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ApicLEVEL = 0x00008000,
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ApicIMASK = 0x00010000, /* [16] Interrupt Mask */
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};
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15
string.c
15
string.c
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@ -23,3 +23,18 @@ memset(void *dst, int c, unsigned n)
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return dst;
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}
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int
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memcmp(const void *v1, const void *v2, unsigned n)
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{
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const uint8_t *s1 = (const uint8_t *) v1;
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const uint8_t *s2 = (const uint8_t *) v2;
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while (n-- > 0) {
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if (*s1 != *s2)
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return (int) *s1 - (int) *s2;
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s1++, s2++;
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}
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return 0;
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}
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