for spinlocks, use gcc intrinsics, but say what they compile to
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					 2 changed files with 21 additions and 21 deletions
				
			
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					@ -27,9 +27,10 @@ acquire(struct spinlock *lk)
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  if(holding(lk))
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					  if(holding(lk))
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    panic("acquire");
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					    panic("acquire");
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  // The xchg is atomic.
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					  // On RISC-V, this turns into an atomic swap:
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  //while(xchg(&lk->locked, 1) != 0)
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					  //   a5 = 1
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  //  ;
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					  //   s1 = &lk->locked
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					  //   amoswap.w.aq a5, a5, (s1)
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  while(__sync_lock_test_and_set(&lk->locked, 1) != 0)
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					  while(__sync_lock_test_and_set(&lk->locked, 1) != 0)
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    ;
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					    ;
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					@ -51,19 +52,18 @@ release(struct spinlock *lk)
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  lk->cpu = 0;
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					  lk->cpu = 0;
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  // Tell the C compiler and the processor to not move loads or stores
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					  // Tell the C compiler and the CPU to not move loads or stores
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  // past this point, to ensure that all the stores in the critical
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					  // past this point, to ensure that all the stores in the critical
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  // section are visible to other cores before the lock is released.
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					  // section are visible to other cores before the lock is released.
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  // Both the C compiler and the hardware may re-order loads and
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  // stores; __sync_synchronize() tells them both not to.
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  // On RISC-V, this turns into a fence instruction.
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					  // On RISC-V, this turns into a fence instruction.
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  __sync_synchronize();
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					  __sync_synchronize();
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  // Release the lock, equivalent to lk->locked = 0.
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					  // Release the lock, equivalent to lk->locked = 0.
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  // This code can't use a C assignment, since it might
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					  // This code can't use a C assignment, since it might
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  // not be atomic. A real OS would use C atomics here.
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					  // not be atomic.
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  // On RISC-V, use an amoswap instruction.
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					  // On RISC-V, this turns into an atomic swap:
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  //asm volatile("movl $0, %0" : "+m" (lk->locked) : );
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					  //   s1 = &lk->locked
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					  //   amoswap.w zero, zero, (s1)
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  __sync_lock_release(&lk->locked);
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					  __sync_lock_release(&lk->locked);
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  pop_off();
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					  pop_off();
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					@ -35,13 +35,13 @@
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#define VIRTIO_CONFIG_S_FEATURES_OK	8
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					#define VIRTIO_CONFIG_S_FEATURES_OK	8
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// device feature bits
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					// device feature bits
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#define VIRTIO_BLK_F_RO		5	/* Disk is read-only */
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					#define VIRTIO_BLK_F_RO              5	/* Disk is read-only */
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#define VIRTIO_BLK_F_SCSI	7	/* Supports scsi command passthru */
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					#define VIRTIO_BLK_F_SCSI            7	/* Supports scsi command passthru */
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#define VIRTIO_BLK_F_CONFIG_WCE	11	/* Writeback mode available in config */
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					#define VIRTIO_BLK_F_CONFIG_WCE     11	/* Writeback mode available in config */
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#define VIRTIO_BLK_F_MQ		12	/* support more than one vq */
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					#define VIRTIO_BLK_F_MQ             12	/* support more than one vq */
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#define VIRTIO_F_ANY_LAYOUT		27
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					#define VIRTIO_F_ANY_LAYOUT         27
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#define VIRTIO_RING_F_INDIRECT_DESC	28
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					#define VIRTIO_RING_F_INDIRECT_DESC 28
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#define VIRTIO_RING_F_EVENT_IDX		29
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					#define VIRTIO_RING_F_EVENT_IDX     29
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struct VRingDesc {
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					struct VRingDesc {
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  uint64 addr;
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					  uint64 addr;
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					@ -49,14 +49,14 @@ struct VRingDesc {
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  uint16 flags;
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					  uint16 flags;
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  uint16 next;
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					  uint16 next;
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};
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					};
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#define VRING_DESC_F_NEXT	1
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					#define VRING_DESC_F_NEXT  1 // chained with another descriptor
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#define VRING_DESC_F_WRITE	2 // device writes (vs read)
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					#define VRING_DESC_F_WRITE 2 // device writes (vs read)
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struct VRingUsedElem {
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					struct VRingUsedElem {
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  uint32 id; // index of start of completed descriptor chain
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					  uint32 id;   // index of start of completed descriptor chain
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  uint32 len;
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					  uint32 len;
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};
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					};
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// for disk ops
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					// for disk ops
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#define VIRTIO_BLK_T_IN		0
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					#define VIRTIO_BLK_T_IN  0 // read the disk
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#define VIRTIO_BLK_T_OUT	1
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					#define VIRTIO_BLK_T_OUT 1 // write the disk
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